AndesCore™ AX45 RISC-V CPU Processor Core

The 64-bit AX45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” Packed-SIMD/DSP instructions, “N” for user-level interrupts and Memory Management Unit (MMU) for Linux support. It issues two instructions per cycle that significantly increases the performance efficiency that is important for many applications. AX45 is also equipped with comprehensive SIMD/DSP instructions that can boost the performance of voice, audio, image and signal processing. Its “FD” extensions support IEEE754-compliance single and double precision floating point instructions as well. It incorporates MemBoost to enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. AX45 features advanced low power branch prediction mechanism for efficient branch execution, instruction and data caches, local memories, and ECC error protection. It also includes vectored and preemptive interrupt controller to serve diversified system events, AXI 64-bit bus, rich power management, and JTAG debug and trace interface for software development support. • 64-bit in-order dual-issue 8-stage pipeline CPU architecture • AndeStar™ V5 Instruction Set Architecture, compliant to RISC-V technology • DSP/SIMD extensions • Floating point extensions • Andes extensions, architected for performance and functionality enhancements • 16/32-bit mixable instruction format for compacting code density • Advanced low power branch predication to speed up control code • Return Address Stack to accelerate procedure returns • Memory Management Unit, Physical Memory Protection, and programmable Physical Memory Attribute • MemBoost for heavy memory transactions • Flexibly configurable Platform-Level Interrupt Controller for supporting range of system event scenarios • Vectored interrupt handling enhancement for real-time performance • Advanced CoDense™ technology to reduce code size