Message-Driven Architecture Exploration for the Heterogeneity Era with MoSAIC
Monday, May 13, 2024 3:00 PM to Wednesday, May 15, 2024 4:00 PM · 2 days 1 hr. (Europe/Berlin)
Foyer D-G - 2nd floor
Research Poster
Beyond Moore's LawEmerging Computing TechnologiesExtreme-scale SystemsHeterogeneous System ArchitecturesMemory Technologies and Hierarchies
Information
Poster is on display and will be presented at the poster pitch session.
This poster showcases MoSAIC, an FPGA-based, full-stack platform to facilitate the evaluation and design space exploration of HMQs in parallel and heterogeneous architectures. Field programmable arrays (FPGAs) provide a cost-effective testbed for hardware exploration. Moreover, we aim at a lightweight, flexible architecture to enable scalability and flexibility. Massive parallelism and extreme heterogeneity are vital to allowing futuristic exascale (10^18 flops-per-second) high-performance computing (HPC). However, as the levels of parallelism (up to 100M cores) and heterogeneity increase, the scalability of shared memory and cache coherence protocols are compromised. Hardware message queues (HMQs) might be essential for practical massive parallelism and extreme heterogeneity because they offer a low-latency direct path for inter-node communication that bypasses expensive cache-coherence protocols. Second and contrary to general-purpose cache-coherence systems, the same HMQ mechanisms can be used for general-purpose cores such as RISCVs or kick-start computation in specialized accelerators such as Fast Fourier Transform.
Contributors:
This poster showcases MoSAIC, an FPGA-based, full-stack platform to facilitate the evaluation and design space exploration of HMQs in parallel and heterogeneous architectures. Field programmable arrays (FPGAs) provide a cost-effective testbed for hardware exploration. Moreover, we aim at a lightweight, flexible architecture to enable scalability and flexibility. Massive parallelism and extreme heterogeneity are vital to allowing futuristic exascale (10^18 flops-per-second) high-performance computing (HPC). However, as the levels of parallelism (up to 100M cores) and heterogeneity increase, the scalability of shared memory and cache coherence protocols are compromised. Hardware message queues (HMQs) might be essential for practical massive parallelism and extreme heterogeneity because they offer a low-latency direct path for inter-node communication that bypasses expensive cache-coherence protocols. Second and contrary to general-purpose cache-coherence systems, the same HMQ mechanisms can be used for general-purpose cores such as RISCVs or kick-start computation in specialized accelerators such as Fast Fourier Transform.
Contributors:
Format
On-site
