Innovation with Load-Store Interconnects (PCIe, CXL, UCIe) in Supercomputing Landscape

High-performance workloads demand heterogeneous processing, tiered memory architecture, infrastructure accelerators such as SmartNICs, long-haul connectivity, and infrastructure processing units to meet the demands of the emerging compute landscape. Applications such as artificial intelligence, machine learning, data analytics, 5G, automotive, and high-performance computing are driving significant changes in the compute landscape. Interconnect is a key pillar in this evolving landscape in general, and for supercomputing in particular. Three load-store I/O interconnects PCI Express® (PCIe®), Compute Express Link TM (CXL TM), and the die-to-die interconnect Universal Chiplet Interconnect Express TM (UCIe TM), developed by three open industry consortia, are driving innovations with an open plug-and-play slot model that is shaping the evolution of the entire compute continuum. PCI-Express continues its journey of more than two decades of doubling the data rate every generation for seven generations in a fully backward compatible manner while making significant protocol enhancements. Compute Express Link, with its memory and coherency semantics has made it possible to pool and share computational and memory resources at the rack level using low-latency, higher-throughput, and memory-coherent access mechanisms. Universal Chiplet Interconnect Express (UCIe) offers seamless integration of heterogeneous chiplets, including memory, along with co-packaged optics that can be used to connect across servers in a Rack and Pod to realize resource sharing and dis-aggregation using CXL protocol. In this talk we will delve into how these protocols are evolving and need to evolve in a complementary manner to enable significant advances in the supercomputing landscape in the future.