International Workshop on Smart Networks, Data Processing and Infrastructure Units
Thursday, May 25, 2023 9:00 AM to 1:00 PM · 4 hr. (Europe/Berlin)
Hall Y11 - 2nd Floor
Workshop
Emerging HPC Processors and AcceleratorsExtreme HeterogeneityManaging Extreme-Scale ParallelismMemory and Storage TechnologyParallel Programming Languages
Information
In recent years, the use of smart network adapters, also known as SmartNICs, has seen a rapid increase. These adapters offer new capabilities for high-performance computing (HPC) beyond standard packet processing. Examples include data processing units (DPUs) or infrastructure processing units (IPUs) that have evolved into system-on-a-chip’s (SoCs) that can include programmable FPGAs, lightweight processing cores and specialized accelerators. DPUs are primarily used for data center operations such as packet filtering, I/O acceleration and security, but there is also growing interest in using them to accelerate HPC applications by offloading communication, I/O management and even part of the application computational workload to them. This workshop brings together experts from the HPC community, including representatives from national laboratories, HPC vendors and international research centers, to share their knowledge and insights on how DPUs can be leveraged to accelerate HPC applications. In addition to presentations on current research and developments, participants will also discuss new trends in DPU design and their potential use cases. Presenters include researchers, tools developers and HPC users, with a keynote speaker to provide an overview of the evolution of SmartNICs and why they are becoming increasingly important in today's computing landscape.
Format
On-site
Targeted Audience
The target audience for this workshop will be HPC users, tool developers, academic researchers, and vendors interested in learning on how to leverage Data Processing and Infrastructure units in their HPC applications and tools eco-systems. Attendees will learn about the new trends in DPU design and their potential use-cases.
Beginner Level
40%
Intermediate Level
40%
Advanced Level
20%
Speakers
Martin Schulz
ProfessorTechnical University of MunichEstela Suarez
ProfessorForschungszentrum Juelich GmbHOscar Hernández
Senior Computer ScientistOak Ridge National LaboratoryRG
Richard Graham
Senior DirectorNVIDIADirk Pleiter
ProfessorKTH Royal Institute of TechnologyPR
Philip Roth
Group LeaderOak Ridge National LaboratoryTobias Weinzierl
ProfessorDurham UniversitySamuel Antao
Senior Member of Technical StaffAMDRichard Vuduc
Associate ProfessorGeorgia Institute of TechnologyRyan Grant
ProfessorQueen's University