NHR Performance Lab
Tuesday, May 31, 2022 9:00 AM to 6:30 PM · 9 hr. 30 min. (Europe/Berlin)
Foyer 3 + H - Ground Floor
Information
To match growing demands for performance and energy efficiency, increasingly heterogeneous architectures are utilized. Code adaptation and target specific optimization are required, but software developers want to implement codes at abstract levels hiding architecture-specific details for better maintainability.
Our PerfLab project addresses these challenges by supporting code developers and users to acquire a deeper understanding of hardware and software interrelationships. The knowledge of suitable modeling methods and tools for target-specific code optimization techniques needs to be extended in the NHR community. Project objects are: (i) deep memory hierarchies in Heterogeneous Memory Systems (HMS), (ii) new execution models with processors and accelerators, and (iii) accelerator integration and offloading. Our current working activities include: (1) evaluation of the extended LIKWID tool for runtime profiling on HMS, (2) performance studies of tools-guided data partitioning in HPC codes, (3) evaluation of an OpenMP compiler prototype with memory management on HMS, (4) performance assessment of GPU Unified Memory in OpenMP/MPI workloads, and (5) code generation for FPGAs and tools-assisted performance analysis.
We extended the capabilities of the LIKWID performance analysis tool with the integration of performance events of selected NVRAM and FPGA technology. For the easy-to-use management of deep memory hierarchies, parallel paradigms in OpenMP are extended and a prototype runtime for different memory architectures is implemented. For FPGA, we demonstrate a code generation pipeline for stencil applications on FPGAs by applying the GHODDESS, pystencils, and StencilStream tools. We further present our training activities and knowledge dissemination strategies for the NHR community.
Contributors:
Our PerfLab project addresses these challenges by supporting code developers and users to acquire a deeper understanding of hardware and software interrelationships. The knowledge of suitable modeling methods and tools for target-specific code optimization techniques needs to be extended in the NHR community. Project objects are: (i) deep memory hierarchies in Heterogeneous Memory Systems (HMS), (ii) new execution models with processors and accelerators, and (iii) accelerator integration and offloading. Our current working activities include: (1) evaluation of the extended LIKWID tool for runtime profiling on HMS, (2) performance studies of tools-guided data partitioning in HPC codes, (3) evaluation of an OpenMP compiler prototype with memory management on HMS, (4) performance assessment of GPU Unified Memory in OpenMP/MPI workloads, and (5) code generation for FPGAs and tools-assisted performance analysis.
We extended the capabilities of the LIKWID performance analysis tool with the integration of performance events of selected NVRAM and FPGA technology. For the easy-to-use management of deep memory hierarchies, parallel paradigms in OpenMP are extended and a prototype runtime for different memory architectures is implemented. For FPGA, we demonstrate a code generation pipeline for stencil applications on FPGAs by applying the GHODDESS, pystencils, and StencilStream tools. We further present our training activities and knowledge dissemination strategies for the NHR community.
Contributors:
- Christian Terboven (Rheinisch-Westfälische Technische Hochschule Aachen)
- Thomas Steinke (Zuse Institute Berlin (ZIB))
- Thomas Gruber (Friedrich-Alexander-Universität Erlangen-Nürnberg)
- Tobias Kenter (Universität Paderborn, Paderborn Center for Parallel Computing)
- Julian Kunkel (Gesellschaft für wissenschaftliche Datenverarbeitung mbH Göttingen)
Format
On-site
