Creating an Open HPC Ecosystem with RISC-V

Technology trends are mandating software/hardware co-design for HPC systems. An Open Standard Instruction Set Architecture (ISA) like RISC-V enables a powerful co-design paradigm. Presently, RISC-V lacks the maturity of other closed ISAs available on the market and many in the HPC community are unfamiliar with the details of RISC-V and/or incorrectly associate the ISA and development efforts as being limited to the embedded community. However, today, there is a focused and dedicated effort is underway within the RISC-V community (well-funded companies, government support, and research) to bring RISC-V into the HPC space. As part of this BoF, we will update the larger community on our efforts (identify the HPC gaps, provide standardized ISA solutions and lead the effort to build up the ecosystem) as well as solicit feedback for prioritization of next steps. First, we will present the status of the current SW and HW RISC-V ecosystem with a focus on HPC (20 minutes) including discussion of our ongoing RISC-V HPC Software testbed. Next, we will have an interactive discussion about the future of RISC-V and HPC with the aim of creating an HPC ecosystem based on Open Source (40 minutes). The latter discussion will include a gap analysis and prioritization of targets in HPC with RISC-V hardware and the associated software.

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Contributors:

• John Davis (Barcelona Supercomputing Center)
• John Leidel (Tactical Computing Labs)
• David Donofrio (Tactical Computing Labs)
• Doug Norton (Inspire Semiconductor)
• Michael Wong (Codeplay)