RISC-V based special-purpose computer for Molecular Dynamics simulations
Monday, June 28, 2021 1:55 PM to 2:15 PM · 20 min. (Africa/Abidjan)
Stream#1
Extreme Heterogeneity
Information
Contributors:
Abstract:
We have successfully developed the MDGRAPE-4A, a special-purpose computer system for molecular dynamics (MD) simulations. For this, the System-on-Chip (SoC) has been designed with parallel cores based on the RISC-V architecture. The RISC-V core has been implemented using Synopsys ASIP designer and the instructions were added for efficient calculations of three-dimensional vectors in 32-bit fixed-point format. Special functions including inverse, inverse square-root and inverse cosine were also implemented. The SoC also integrates the dedicated pipelines for nonbond forces, a network unit, and memories. The SoC accelerate simulation by adding hardware for charge assignments and back interpolation, convolution calculations for long-range electrostatics, particle management units in memory blocks, and so on. The system consists of 512 SoCs with three-dimensional torus optical network. We have ported GROMACS for it, and current performance is about 1 microsecond per day for the system of 100K atoms. The design of the next-generation hardware for MD simulations was started recently using the Chisel language and Chipyard environment. Currently, we are rewriting the RTL and basic library in Chisel3. It will enable extended design-space exploration and bring better performance in future.
Abstract:
We have successfully developed the MDGRAPE-4A, a special-purpose computer system for molecular dynamics (MD) simulations. For this, the System-on-Chip (SoC) has been designed with parallel cores based on the RISC-V architecture. The RISC-V core has been implemented using Synopsys ASIP designer and the instructions were added for efficient calculations of three-dimensional vectors in 32-bit fixed-point format. Special functions including inverse, inverse square-root and inverse cosine were also implemented. The SoC also integrates the dedicated pipelines for nonbond forces, a network unit, and memories. The SoC accelerate simulation by adding hardware for charge assignments and back interpolation, convolution calculations for long-range electrostatics, particle management units in memory blocks, and so on. The system consists of 512 SoCs with three-dimensional torus optical network. We have ported GROMACS for it, and current performance is about 1 microsecond per day for the system of 100K atoms. The design of the next-generation hardware for MD simulations was started recently using the Chisel language and Chipyard environment. Currently, we are rewriting the RTL and basic library in Chisel3. It will enable extended design-space exploration and bring better performance in future.
