Workshop on Software Co-Design Actions in European Flagship HPC Codes

Thursday, June 2, 2022 2:00 PM to 6:00 PM · 3 hr. 59 min. (Europe/Berlin)
Hall Y12 - 2nd Floor
AcceleratorsExascale SystemsPerformance Modeling & TuningHeterogeneous HPC Technologies and their Programming Challenges


This mini-workshop will bring together representatives from the European Centres of Excellence in HPC applications (EU HPC CoE) and key European HPC stakeholders to share with an international and engaged audience their lessons learnt and experiences in software co-design. Co-design has been long debated by the HPC community, and can be credited with some impressive results. This workshop focuses specifically on software co-design actions applied on production-grade community-wide European flagship HPC applications. Any contribution highlighting co-design activity involving standalone CPU, accelerators like GPU and the role CPU and accelerators play together is welcome. Innovations in scalable algorithms and computational methods are enabling richer and more fruitful codesign activities beyond simply “improving vectorization” or "porting everything to the GPU". The current HPC technology landscape is complex and dynamic with a rich portfolio of choices across CPU architecture and accelerators. Software that leverages every component of a heterogeneous HPC solution has a key role to play in unlocking the next level of application performance. Such software is best realized via co-design. Workshop attendees will learn from application developers and computational scientists about their software journey to prepare ahead of time their HPC codes for EuroHPC European Pre-Exascale and Exascale systems.

  • Filippo Spiga (NVIDIA Ltd)
  • Jean-Marc Denis (SiPearl)
  • Guy Londsale (scapos AG)
  • Conrad Hillairet (Arm Ltd)