Compiler-assisted Correctness Checking and Performance Optimization for HPC
Thursday, June 2, 2022 2:00 PM to 6:00 PM · 3 hr. 59 min. (Europe/Berlin)
Hall Y8 - 2nd Floor
HPC Workflows
Information
Practical compiler-enabled programming environments, applied analysis methodologies, and end-to-end toolchains can contribute significantly to performance portability in the exascale era. The practical and applied use of compilation techniques, methods, and technologies, including static analysis and transformation, are imperative to improve the performance, correctness, and scalability of high-performance applications, middleware, and reusable libraries.
This workshop brings together a diverse group of researchers with a shared interest in applying compilation and source-to-source translation methodologies, among others, to enhance explicit parallel programming such as MPI, OpenMP, PGAS, and hybrid models, but also heterogeneous programming on GPUs and FPGAs.
For the third year, this workshop seeks innovative applications of such technologies singly and in combination to derive enhanced utility in parallel programs that are generalizable beyond a single case study or narrow application. Original papers will identify and solve challenges in the tradeoffs of scalability, performance, predictability, correctness, productivity, and portability on-node and at massive scale; strong-scaling, weak-scaling, and hybrid-scaling solutions assisted, augmented, and/or enabled by compiler technology are in scope. Topics of interest include but are not limited to: correctness checking of parallel programs, source-to-source translation of legacy MPI codes to improve performance-portability, instrumentation, and massively multipass FPGA compiler optimization strategies.
Organizers:
This workshop brings together a diverse group of researchers with a shared interest in applying compilation and source-to-source translation methodologies, among others, to enhance explicit parallel programming such as MPI, OpenMP, PGAS, and hybrid models, but also heterogeneous programming on GPUs and FPGAs.
For the third year, this workshop seeks innovative applications of such technologies singly and in combination to derive enhanced utility in parallel programs that are generalizable beyond a single case study or narrow application. Original papers will identify and solve challenges in the tradeoffs of scalability, performance, predictability, correctness, productivity, and portability on-node and at massive scale; strong-scaling, weak-scaling, and hybrid-scaling solutions assisted, augmented, and/or enabled by compiler technology are in scope. Topics of interest include but are not limited to: correctness checking of parallel programs, source-to-source translation of legacy MPI codes to improve performance-portability, instrumentation, and massively multipass FPGA compiler optimization strategies.
Organizers:
- Julien Jaeger (CEA)
- Emmanuelle Saillard (INRIA)
Format
On-site
