AndesCore™ AX45MP Multicore RISC-V CPU Processor Core

AndesCore™ AX45MP Multicore RISC-V CPU Processor Core

IP

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AndesCore™ AX45MP 64-bit multicore CPU IP is an 8-stage superscalar processor based on AndeStar™ V5 architecture. It supports RISC-V standard “G (IMAC-FD)” extensions, “C” 16-bit compression instructions, DSP/SIMD ‘P’ extension (draft), user-level interrupt ‘N’ extension, and Andes performance/ functionality enhancements for faster memory accesses and branch handling. Andes Custom Extension™ adds user-defined instructions. An MMU supports Linux based applications, branch prediction for efficient branch execution, level-1 instruction/data caches and local memories for low-latency accesses. The 4-core AX45MP symmetric multiprocessor supports a level-2 cache controller with instruction and data prefetch. Coherence manager implements MESI protocol to handle level-1 cache coherence, including I/O coherence for cacheless bus masters. Other features include ECC for level-1/2 memory soft error protection, Platform-Level Interrupt Controller with enhancements for vectored dispatch and priority-based preemption, CoDense™, StackSafe™ for software quality, and QuickNap™, PowerBrake, and WFI for power management. • 64-bit in-order dual-issue 8-stage pipeline CPU architecture • 4-core Symmetric multiprocessing • Level-2 cache and cache coherence support • AndeStar™ V5 Instruction Set Architecture. Compliant to RISC-V ISA IMACFDN, with Andes performance/functionality extensions • Floating point extension DSP/SIMD ISA • Andes Custom Extension™ for customized acceleration • 64-bit architecture for memory space over 4GB • 16/32-bit mixable instruction format for compacting code density • Branch predication • Return Address Stack • Memory Management Unit, Physical Memory Protection and programmable Physical Memory Attribute • Level-1 and level-2 cache controllers with 64-byte cache line size • Flexibly configurable Platform-Level Interrupt Controller for range of system event scenarios • Vectored interrupt handling enhancement • Advanced CoDense™ technology to reduce code size
ANDES TECHNOLOGYSixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and continues to rise. To the end of 2020, the cumulative volume of Andes-Embedded™ SoCs has reached 7 billion.  

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