AndesCore™ NX45 RISC-V CPU Processor Core

The 64-bit NX45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, and “N” for user-level interrupts. It issues two instructions per cycle that significantly increases the performance efficiency that is important for many applications. Its “FD” extensions support IEEE754-compliance single and double precision floating point instructions as well. It incorporates MemBoost to greatly enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. In addition, NX45 features advanced low power branch prediction mechanism for efficient branch execution, instruction and data caches, local memories, and ECC error protection. It also includes vectored and preemptive interrupt controller to serve diversified system events, AXI 64-bit bus, rich power management, and JTAG debug and trace interface for software development support. • 64-bit in-order dual-issue 8-stage pipeline CPU architecture • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology • Floating point extensions • Andes extensions, architected for performance and functionality enhancements • 16/32-bit mixable instruction format for compacting code density • Advanced low power branch predication to speed up control code • Return Address Stack (RAS) to accelerate procedure returns • Physical Memory Protection(PMP), and programmable Physical Memory Attribute (PMA) • MemBoost for heavy memory transactions • Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios • Enhancement of vectored interrupt handling for real-time performance • Advanced CoDense™ technology to reduce program code size