Speedcore™ eFPGA IP

Speedcore™ embedded FPGA (eFPGA) IP has brought the power and flexibility of programmable logic to ASICs and SoCs. Customers can integrate a Speedcore eFPGA into an SoC for high-performance, compute-intensive and real-time processing applications such as AI, machine learning, 5G wireless, networking and automotive. What is an eFPGA? An embedded FPGA (eFPGA) is an FPGA IP core that is embedded within a custom SoC or ASIC device. The IP can be licensed for use similar to that of other IP used in semiconductor designs. Unlike the design process for a standalone FPGA, eFPGA designers can select the exact amount of logic, DSP and memory resources required for their customer's application. An eFPGA can also be used to lower system cost, power and board space by eliminating the standalone FPGAs when moving into high-volume production. Highlights * Speedcore™ Embedded FPGA (eFPGA) IP – The only eFPGA technology shipping in high-volume production applications: – Customer-defined eFPGA resource counts for logic, embedded memory blocks, MLP and DSP blocks – Logic – 6-input look-up-tables (LUTs) plus integrated wide MUX functions and fast adders – Logic RAM – 2 kb per memory block for LRAM2k, and 4kb per memory block for LRAM4k – Block RAM – 72 kb per memory block for BRAM72k, and 20kb per memory block for BRAM20k – DSP64 – 18 × 27 multiplier, 64-bit accumulator and 27-bit pre-adder per block – Machine learning processors (MLP) – 32 multiplier/accumulators (MACs) per block, supporting integer and floating point formats * Achronix delivers the eFPGA IP as a hard macro in GDSII format. * Speedcore IP is available on the following nodes: – TSMC 16FFC – TSMC 12FFC – TSMC 7nm FinFET – Speedcore IP can be ported to other process nodes * Speedcore performance: – Max: 750 MHz – Typical: 300 MHz to 500 MHz * Lowest latency interface: – One stage of latency between a Speedcore instance and the host SoC